A method of dividing the gene dropping algorithm for estimating allelic probabilities in pedigree data into two stages is described. Each stage can be implemented on a field programmable gate array (FPGA), with only two wires required between the two FPGA. As the approach effectively removes the need for temporary storage, it allows the processing of pedigrees of larger size than those feasible with a single FPGA. The amount of increase in feasible size is dependant on the amount of storage required for observed genotypes and stored solutions relative to the storage required for pedigree connections. The approach allows pipelining of the gene drop algorithm over multiple FPGA, with a gene drop sample for the whole pedigree produced for every clock cycle.
Proceedings of the World Congress on Genetics Applied to Livestock Production, Volume , , 26.09, 2006
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